This is a complement phase inverter circuit. Sometimes this circuit called a paraphase amplifier circuit. This circuit has two output signals that is have sufficient “headroom” because this circuit is biased. The transistor will be saturated when the collector decreases, the emitter voltage increases and set the limit. Here is the circuit:
This circuit can produces a peak to peak output about 5V because 5 V between collector and emitter is allowed when resting. When this circuit need a high input impedance, the bias divider value should be increased by factor of 10.