PLL Lock Detection

In some PLL application, sometimes we need to provide lock indication when the PLL is in locked state. The simplest one is binary indication, 0 or 1 to correspond with lock/unlock condition. This  condition should be easy to be presented with a LED lamp.


The schematic diagram  shows a lock-detection scheme for the CD4046B.  The PLL system uses phase comparator II; the VCO bandwidth is set up for an fmin of 9.5 kHz and an fmax of 10.5 kHz.  The signal input is switched between two discrete frequencies of 20 kHz and 10 kHz. Therefore, the PLL locks and unlocks on the 10-kHz and 20-kHz signals, respectively. When the
PLL is in lock, the output of phase comparator I is low, except for some very short pulses that result from the inherent phase difference between the signal and comparator inputs; the phase-pulses output (terminal 1) is high, except for some very small pulses resulting from the same phase difference.  [Circuit’s schematic diagram source: Texas Instruments Application Report]