Free Circuit Diagram

The schematic diagram below shows a very simple sample-and-hold circuit using the CA3140 as the readout amplifier for the memory capacitor. The CA3080A is used as both input buffer amplifier and low feed-through transmission switch. System offset nulling is provided for CA3140 via its offset nulling pins. A load simulation of 2k and 30pF is shown in the schematic , connected using dotted lines.

In the circuit, the storage capacitor (C1)  value is only 200pF. Larger value capacitors gives longer “hold” periods but with slower slew rates. The slew rate is:

(dv/dt)=(I/c)=(0.5mA/200pF)=  (2.5V/us)

Pulse “droop” during the hold interval is 170pA/200pF which is 0.85uV/us (i.e., 170pA/200pF), this 170pA represents the typical leakage current of the CA3080A when strobed off.  If we increased  C1 to 2000pF, the “hold-droop” rate will decrease to 0.085uV/us, and the slew rate would decrease to 0.25V/us. The parallel diode network connected between pin 3 of the CA3080A and pin 6 of the CA3140 prevents large input signal feed-through across the input terminals of the CA3080A to the 200pF storage capacitor when the CA3080A is strobed off. [Circuit's schematic diagram source: Intersil Application Notes]

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