There are several integrated circuit chips designed specially for LDO (low drop out) voltage regulator. Building LDO using standard op-amp and discrete components can be an alternative. Here is one design of LDO circuit:

Low drop out LDO voltage regulator using discrete semiconductors circuit schematic

Here some guidelines to select the components values:

  • D1 is chosen for the best performance, the sharper the on-off transition curve the better. Some people say that 5,6V Zener diode has better voltage regulation than other voltage. But you can actually use any voltage below the expected minimum output voltage. The output voltage will be Vd(R4+R3)/R3, with Vd is the voltage of the Zener diode D1.
  • R1 is selected so the exact voltage of D1 will have minimum drift over the input supply range variation.  Look at the D1 datasheet. R1 is usually not critical, and you can use larger value to save the current loss.
  • R3 and R4 uses to set the expected output voltage, and are chosen as large as possible to conserve the current loss, but should be much smaller than the op-amp’s input impedance.
  • Q1 is chosen for the lowest Vce drops for the best performance, the higher gain (hFe), and the collector current must be capable to handle the expected maximum load current.
  • Q2 must have low drop Vce if the regulator is expected to regulate low voltage source, but not so critical if the input supply voltage is high.
  • R2 can be selected to make sure that Q2 is always “on” even when the regulator is unloaded.  Just remember that the voltage across R2 is same with Vbe of Q1, you can set the value of R2 to set the current Ice of Q2 at the best  of Q2’s Ibe/Ice curve.
  • Select The op-amp A1 for the best high gain, highest input impedance. The most important character for A1 is that the output swing should be capable to go down below  Q2 Vbe turn-on point.

[Schematic diagram source: NXP Application Note]