This voltage regulator circuit gives a stable 5V output from unregulated inputs (more than 5V). The stability of the output voltage is good enough, only change less than 0.1 volts when the load current changes about 60mA. Here is the schematic diagram of the circuit:
The basic principle of the voltage regulation rely on the mechanism of keeping the the FET’s gate voltage at the cut-off point. The FET’s gate volage is the voltage across R2. At zero volt (when there is no current flowing through R2), the FET will be conducting, and a small current at FET (Tr1) will cause much larger current to flow through Tr3. This current will flow through R2 and the gate voltage becomes negative. A some level the negative voltage at FET’s gate will cut-off the FETs current and keep the output voltage stable.
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